As complementary metal-oxide-semiconductor (CMOS) technology has developed, it has become the technology of choice for integrated circuitry due to its capability to produce low-cost, low-power, reliable and highly integrated systems. Ever-increasing device densities have been driven by demand for ever-increasingly capable consumer products that require more and more memory to support ever more complex circuitry for process and control systems. One of the more recent applications to be effectively addressed by CMOS technology has been that of imaging. This has been accomplished by the development of active pixel detectors which incorporate the transistors of the readout electronics into the same device cell as the sensor itself.
Unfortunately, imagers with photodiodes and CMOS integrated on a single semiconductor substrate, or wafer, are difficult to manufacture. The photodiode and the CMOS can each interfere with the other and limit overall performance. When a viable compromise in performance is achieved in a monolithic photodiode with CMOS imager, there is the opportunity to scale it to smaller feature size consistent with industry standard technology migration. This yields the required economic competitiveness and performance improvement but scaling is limited by an accompanying reduction in voltage range and an increase in noise level. Thus, it would be an advancement in the art to provide a monolithic sensor cell that—                integrates photodiodes and CMOS without compromising the performance of either component,        reduces the voltage limitations associated with scaling,        improves the noise performance, and        implements efficient fabrication techniques.        
Some early attempts to produce integrated CMOS-based imagers used a bulk-CMOS technology in which reverse-biased photodiodes formed by the n+/p− substrate junction relied upon a portion of the substrate as a collection region. For a while, this conveniently allowed arrays of photodiodes to scale downward in size as CMOS densities increased. This was a workable technique as long as the device dimensions and corresponding collection regions were somewhat larger than the wavelengths of the photons being detected. However, for detectors in the visible region of 400-800 nanometers (nm), the collection efficiency dropped off and crosstalk between cells increased as CMOS dimensions dropped below about 0.5 μm.
The advent of Silicon-on-Insulator (SOI) and its application to CMOS technologies has presented alternatives to bulk-CMOS. In SOI, transistors are created on a thin top silicon layer that is separated from a silicon substrate by a thin insulating layer of glass or silicon dioxide. Standard SOI substrates are constructed by one of two processes. In the first of the two processes, known as SIMOX (for Separation by IMplantation of OXygen), oxygen is ion-implanted into a polished wafer under intense heat after which the wafer is annealed in high temperature to form a buried oxygen layer, commonly known as the BOX, at a uniform depth from the surface while eliminating defects made in the surface layer. In the second of the two processes, a “Bonded” SOI wafer is produced by bonding of a thin device wafer onto a thicker one known as a handle wafer utilizing for adhesion the common oxide that becomes the BOX. Both processes result in the same three-layer substrate structure. The result of either process is an SOI wafer having a thicker base substrate, or handle layer, on top of which is a buried oxide layer which in turn is covered by the thinner SOI layer. Thicknesses of the layers for present production technologies are about 0.1-1 μm for the SOI layer, 0.1-1 μm for the BOX, and 750 μm for the handle layer.
With the buried oxide layer providing isolation between the SOI layer and the substrate, devices built in the SOI layer experience reduced substrate capacitance which contributes to lower power requirements while increasing transistor switching speed. Also, the I.sub.O versus V.sub.G characteristics of such devices have steeper slopes below V.sub.t than conventional bulk-CMOS devices, thus reducing leakage current when devices are in their off-states without the need to increase threshold voltages.
As attractive as SOI-CMOS device characteristics may be for imagers, the use of this technology for such an application is not without its drawbacks. A temptation to construct photodetectors in the SOI layer is met with the recognition that the thin silicon film lacks sufficient thickness to efficiently absorb photons of visible light. For detection of light having a wavelength of 800 nm, for instance, the quantum efficiency of a 0.5 μm thick silicon film is only about 5%, whereas a film having a thickness of 16 μm or greater is required to achieve a more desirable quantum efficiency of 80%. This suggests that a more desirable solution would be to form the detectors in the thicker handle layer, while preserving the SOI layer for the readout circuitry. Earlier versions of this approach have been described by others.
The formation of photodiodes in a silicon substrate with MOS transistors built in the thin silicon-on-insulator layer has been described by Akimoto, et al. in U.S. Pat. No. 4,954,895. In their design a photodiode which was formed in the substrate also served as the source terminal of a vertical MOS transistor switch, the gate and drain of which were formed on the silicon substrate. These in turn were connected to horizontal MOS transistors in an SOI structure formed on an insulating oxide film for the remainder of the readout circuitry.
Pain and Zheng as co-inventors in U.S. Pat. Nos. 6,380,572 (to Pain, et al.) and 6,838,301 (to Zheng, et al.) described the formation of silicon islands on top of the buried oxide layer on the substrate. The BOX was then etched away to provide access for formation of the photodetector. In this manner processing of the photodetector could be accomplished simultaneously with implementation of the drain and source of the first MOS device at the input of the readout circuitry in the SOI layer.
An approach related to the above-described techniques is developed by Kucewicz, et al. in a paper entitled “Development of monolithic active pixel detector in SOI technology” (Nuclear Instruments and Methods in Physics Research Section A, Volume 541, Issues 1-2, 1 Apr. 2005, Pages 172-177). Unlike others who have aimed specifically at photo detection, the focus of Kucewicz, et al. is to develop sensors for ionizing radiation such as that from a Strontium-90 (Sr-90) radioactive source. Their preference is to use wafer-bonded substrates, rather than other popular SOI substrates obtained in the SIMOX process, due to what they identify as the lower level of structural defects in both device and support layer and the absence of silicon inclusions and islands in the buried oxide. Otherwise, their approach is very similar to those that have been described above. Their particle detecting sensor, having a depth of 300 micrometers, is realized in the support layer with its high-resistivity (44 k Ohm/cm) and has a conventional form of a matrix of p+−n junctions. The readout electronics is fabricated in the 1.5 μm thick, low-resistive device layer and monolithically coupled to the detector by a connection that passes through the buried oxide.
One feature that is common to all of the above described implementations is that both the SOI and buried oxide (BOX) layers are etched away to open a window in which to build the sensor in the handle layer, with the readout electronics in the SOI layer. The present invention, to be described here, is unique in that it utilizes a process that does not etch but maintains the integrity of the BOX. This new method provides the advantages of isolation between the components fabricated in each of the two layers and protection of the surface of the photodiode from damage or contamination. This process invention also provides for re-planarization of the silicon surface prior to CMOS processing. Furthermore, the high temperature processing desired for construction of photodiodes is completed prior to the CMOS processing, thereby permitting nanoscale CMOS to be integrated with the photodiodes.
Another significant advantage of the process used in the present invention is that it is fully compatible with the Flexfet™ process developed and owned by American Semiconductor Incorporated and described by Hackler, et al. in U.S. patent application Ser. No. 10/613,169, which will be referred to as the '169 application. The addition of only two minor divergences from the Flexfet™ process allows the readout electronics of the present invention to take full advantage of the Flexfet™ devices produced in that process. Thus, in accord with the stated objectives, an efficient fabrication technique integrates photodiodes and CMOS without compromising the performance of either component. The process used to develop the sensor is completely decoupled from the CMOS process.
Furthermore, the resulting monolithic sensor cell of the present invention makes full use of unique double-gated Flexfet™ transistors in the readout circuitry to reduce the voltage limitations associated with scaling while at the same time improving noise performance over previous designs. The present invention therefore meets the above-itemized goals, achieving performance that is superior to previous designs through techniques that will now be described and claimed herein.